Parallel Fault Simulation of Digital Circuits

A new approach to parallel fault simulation for sequential circuits based on Binary Decision Diagrams (BDD) is proposed. The efficiency of BDDs for simulation is well known. However, traditional BDDs are not well-suited for fault simulation. Furthermore, up to now, they have not been used for parallel simulation. In the paper, a new class of BDDs is presented, called Structurally Synthesized BDDS (SSBDD). Sequencial circuits are represented as a network of SSBDDs. SSBDD networks allow efficient and compressed fault modeling. An algorithm is developed and implemented for parallel fault simulation based on the new SSBDD model.